Description
Verilog HDL is a language for digital design engineers that is used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL (Hardware Description Language) with a user community of more than 50,000 active designers. Palnitkar covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis.
