About the Author
SAMIR PALNITKAR is the president of Indus Consulting Services, Inc., a company which specializes in providing training and consulting resources for microprocessor, ASIC and EDA engineering.
Indus provides engineering resources for behavioral and RTL Verilog modeling, logic synthesis, timing analysis, Verilog PLI, setup of verification environment and development of diagnostics. Training courses are offered for Verilog HDL, verification, logic synthesis and Verilog PLI.
Samir has consulted with a variety of EDA companies and design houses for verification, logic synthesis, RTL coding, static timing analysis and hardware acceleration. Prior to Indus, the author was a Member of Technical Staff at Sun Microsystems, Inc. in Mountain View, CA. His activities included digital design verification, modeling of shared memory multiprocessor architectures, Verilog HDL and logic synthesis based design methodologies, and investigation of new EDA tools and technologies. He was also an internal consultant on several microprocessor and ASIC design projects.
Mr. Palnitkar holds a Bachelor of Technology in Electrical Engineering from Indian Institute of Technology, Kanpur, a Master's in Electrical Engineering from University of Washington, Seattle and an MBA degree from San Jose State University, San Jose, CA.
