Sun XVR-4000 Graphics Accelerator - Detailed View

No Longer Orderable
This product has reached end-of-life and is no longer orderable.

• Overview
• Product Family Placement
• Key Users
• Key Industries
• Enabling Technology and Features

Overview

The Sun XVR-4000 graphics accelerator provides excellent visual quality of rendered images through sophisticated, programmable, anti-aliasing filter chips built onto the card as well as increased color precision with 10-bit per color. Ideal for industries and markets that include manufacturing, automotive and aerospace, oil and gas, research, education, and defense, the Sun XVR-4000 graphics accelerator delivers exceptional performance for the price, high visual quality for users requiring large-screen, collaborative visualization, and extended flexibility and functionality that helps to lower cost of ownership.

Key features of the Sun XVR-4000 graphics accelerator include:

• 144 MB of frame buffer memory
• 1 GB (4 x 256 MB) of texture memory
• Anti-aliasing through dedicated, 5 x 5 programmable radial filter chips
• Maximum 3-D resolution of 1920 x 1200 @ 75 Hz with 4 samples/pixel or 1280 x 1024 @ 75 Hz with 8 samples/pixel
• Maximum 3-D stereo resolution of 1280 x 1024 @ 112 Hz with 4 samples/pixel
• Multidisplay capability at dual 1280 x 1024 @ 75 Hz with 4 samples/pixel or dual 1280 x 1024 @ 112 Hz (non-aliased stereo)
• Dynamic video resizing for guaranteed frame rates
• S-video output for recording entire displays in NTSC/PAL format
• Stereo, framelock, and genlock support

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Product Family Placement

The Sun Fire XVR-4000 graphics accelerator is ideal for use with the Sun Fire V880z visualization server. The Sun Fire V880z visualization server supports up to two Sun XVR-4000 graphics accelerators. The Sun Fire V880z visualization server with the Sun XVR-4000 graphics accelerator complements the Sun Blade 2000 system with Sun XVR-1000 or Sun XVR-1200 graphics accelerators.

The Sun Fire V880z system is ideal for immersive 3-D environments such as CAVE (CAVE Automatic Virtual Environment) or for multichannel, large screen environments (flat or curved) in small or large workgroups, while the Sun Blade 2000 system is ideal for users who need to visualize large datasets at their desks or workstations in a personal visualization environment.

The following table highlights some key features between a Sun Fire V880z system and a Sun Blade 2000 system.

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Key Users

The Sun XVR-4000 graphics accelerator is ideal for high-end users of visualization technology who tend to use stereo glasses, 6 degree-of-freedom trackers, and haptic devices in 3-D environments such as an immersive deskside or CAVE or in multichannel, large screen environments.

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Key Industries

The Sun XVR-4000 graphics accelerator is ideal for markets such as:

• Manufacturing
• Automotive and aerospace
• Oil and gas
• Scientific research
• Education
• Government defense
• Life sciences and pharmaceuticals

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Enabling Technology and Features

Master Chip DMA Engine
Also connecting directly to the Sun Fireplane interconnect and located on the Sun XVR-4000 graphics accelerator, the master chip performs direct memory access (DMA) from the host to fetch command and graphics data streams. The master chip reads data directly from host memory using DMA, gathers it into buffers, and load balances graphics streams to the four parallel rendering pipelines within the Sun XVR-4000 graphics accelerator, thereby interfacing directly with the four MAJC-5200 processors. The master chip also controls all chips on the Sun XVR-4000 graphics accelerator, providing for synchronization as necessary.

MAJC 5200 Processor Chip
Within each rendering pipeline in the Sun XVR-4000 graphics accelerator, the MAJC-5200 processor chip performs transforming, clipping, lighting, and other general-purpose processing. The MAJC-5200 processor chip contains a geometry data preprocessor and two processing units (consisting of four function units each), running at 341 MHz.

FBC3 ASIC
Composed of four major interfaces, the FBC3 ASIC rasterizer performs 2-D and 3-D rasterization, 2-D and 3-D texturing, pixel transfers, and imaging and fragment processing. The FBC3 ASIC rasterizer can write two 66-bit pixels (or samples) in a single frame buffer clock (166 MHz) and can read four pixels (or samples) in two frame buffer clocks.

Texture Buffer Memory
Texture buffer memory consists of eight SDRAMs with a total capacity of 256 MB within each rendering sub-unit, which is used to store texture maps, image processing buffers, and accumulation buffers. Texture memory can also be combined to support larger textures of up to 1 GB in size for volume visualization applications that use the Sun OpenGL targeted extension.

Scheduler Chips
Two scheduler chips route image samples produced by any of the FBC3 rasterizer outputs to any pixel interleave of the sample buffer. As a controller of the 3DRAM64 chips, the scheduler chips also respond to requests from the convolve chips for streams of samples to be sent out over the 3DRAM64 video output pins to parallel convolve chips that generate the video output.

3DRAM64 Chips
Each 3DRAM64 chip integrates DRAM and an SRAM cache on a single chip along with pixel processors and an on-chip arithmetic logic unit (ALU). Since the ALU is implemented directly on the 3DRAM64 chip, the read-modify-write cycles caused by Z-buffering, alpha blending, and stenciling are performed completely inside the 3DRAM64 chip.

Sample Buffer
The sample buffer consists of 32 3DRAM64 chips organized into eight independent interleaves of four chips each. Logically, the sample buffer is organized as a two-dimensional raster of lists of samples. The list order of a sample implies its sub-pixel location. The memories are interleaved per sample so that adjacent samples in a list are in different 3DRAM64 packages.

Route Chips
The 640 outputs of the sample buffer feed into an array of 10 route chips. Each route chip is a 2-bit slice of a router function, connects to two output data pins from each of the 32 3DRAM64 chips, and can redirect this data to any of four convolve chips attached.

Convolve Chips
Four convolve chips perform the reconstruction and band limited reconstruction filtering of the raster stream of samples, providing pixels that are fed into the next convolve chip before final video output. The final video stream is assembled as video is passed from chip to chip, with each convolve chip inserting its portion of each scan line into the aggregate stream. The last chip delivers the complete video stream as well as an optional second stream. The 5 x 5 filter size also implies that each sample will potentially be used in up to 25 different pixel computations. To avoid re-fetching samples from off-chip, six swath lines worth of sample data is cached on each convolve chip.

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