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64-bit data addressing, four-way superscalar, 14 stage non-stalling pipeline, speculative execution, on-chip memory controller and L2 tags, up to 8 MB external L2 cache, advanced process technology including copper interconnects, low-k interlayer dialectric.
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Enables the processor, applications, and operating systems to utilize larger amounts of physical memory, lower memory latencies, improve signalling, and reduce power consumption. VIS Instruction Set allows for easy manipulation of graphical and networking data.
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New architectural features designed to improve overall system performance on an application level.
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