|
|
Architecture
|
- 64-Bit SPARC architecture
- VIS Instruction Set
- Transistor Count: 11 million logic, 12 million RAM, 6 million miscellaneous
- 4-way superscalar
- 14-stage non-stable pipeline
|
|
Process Technology
|
- CMOS .13 micron process
- 1368 pin flip-chip ceramic Land Grid Array (LGA)
|
|
Interconnect
|
Sun Fireplane Interconnect running at 150 MHz
|
|
 Back to top
|
L1 Cache
|
- 64 KB 4-way data
- 32 KB 4-way instruction
- 2 KB Write, 2 KB Prefetch
|
|
L2 Cache
|
- Up to 8 MB External
- On-chip controller and address tags
|
|
Back to top
|
Max Memory
|
16 GB memory subsystem per processors
|
|
Memory Controller
|
On-chip memory controller capable of addressing up to 16 GB of main memory at 2.4 GB/s
|
|
Back to top
|
Power Consumption
|
Power Dissipation: 53 watts at 1.2 GHz
1.6 volt core voltage
|
|
Back to top
|
|
