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Overview

32 Threads in 2 Square Inches

The UltraSPARC T1 processor with CoolThreads technology is the highest-throughput and most eco-responsible processor ever created. It's a breakthrough discovery for reducing data center energy consumption, while dramatically increasing throughput. Its 32 simultaneous processing threads, drawing about as much power as a light bulb, give you the best performance per watt of any processor available.

CoolThreads Technology: a Breakthrough Discovery that Sets the New Standard for the Shared Enterprise

Until now, two threads per core or two cores per processor was the best you could get for mainstream, commercial computing. Now, the UltraSPARC T1, with its onboard memory subsystem, changes everything. The UltraSPARC T1 processor gives you up to eight processing cores with four threads per core. It's like a rack of servers on one chip. With up to 32 simultaneous threads in one incredibly low-power, low-heat processor, you gain the high-volume throughput you need, while saving millions on power and cooling costs. The new standard is here, get ready to move ahead - faster and cooler than ever before.

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Performance and Power

The UltraSPARC T1's massive multithreading-32 simultaneous threads* on just two square inches of silicon-sets new industry performance standards for multiple, single-thread applications and intensively multithreaded applications.

*The threading model is a fine-grain interleave of 32 Light Weight Processes (LWPs) on eight 6-stage pipelines, all 32 threads can have instructions in the process of executing simultaneously.

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Reliability

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Investment Protection

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CPU

• UltraSPARC Architecture 2005 (SPARC V9 compliant)
• On-chip level 2 cache
• Public key encryption support (RSA)
• 48-bit virtual, 40-bit physical address space
• Support for four page sizes: 8K, 64K, 4M, 256M
• Support for Hypervisor
• 4, 6, or 8 core versions

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Caches

• 16 KB primary instruction cache per core
  - Parity protected and single-bit error recoverable
  - 4-way set-associative
  

• 8 KB primary data cache per core
  - Parity protected and single-bit error recoverable
  - 4-way set-associative
  

• 3 MB unifed level 2 cache
  - 12-way set associative, 4 banks
  - ECC
  

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Integration

• Up to 8 cores, 4 threads per core
• 4 144-bit DDR2-533 SDRAM interfaces
  - Quad error correct, octal error detect, chipkill ECC
  
• 4 DIMMS per controller - 16 DIMMS total
• Optional 2-channel operation mode
• JBUS Interface
  - 3.1 GB/sec peak effective bandwidth
  - 128 bit address/data bus
  - 150 - 200 MHz operation
  

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Technology

• .09 micron, 9-layer Cu metal, CMOS process
• 1.0 GHz and 1.2 GHz frequency
• 72 watt typical, 79 watt peak power consumption

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Product Family Positioning