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Tech Specs
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Specifications
Key Specifications
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16 KB primary instruction cache per core
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3 MB unifed level 2 cache
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Up to 8 cores, 4 threads per core
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CPU
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- UltraSPARC Architecture 2005 (SPARC V9 compliant)
- On-chip level 2 cache
- Public key encryption support (RSA)
- 48-bit virtual, 40-bit physical address space
- Support for four page sizes: 8K, 64K, 4M, 256M
- Support for Hypervisor
- 4, 6, or 8 core versions
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Caches
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- 16 KB primary instruction cache per core
- Parity protected and single-bit error recoverable
- 4-way set-associative
- 8 KB primary data cache per core
- Parity protected and single-bit error recoverable
- 4-way set-associative
- 3 MB unifed level 2 cache
- 12-way set associative, 4 banks
- ECC
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Integration
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- Up to 8 cores, 4 threads per core
- 4 144-bit DDR2-533 SDRAM interfaces
- Quad error correct, octal error detect, chipkill ECC
- 4 DIMMS per controller - 16 DIMMS total
- Optional 2-channel operation mode
- JBUS Interface
- 3.1 GB/sec peak effective bandwidth
- 128 bit address/data bus
- 150 - 200 MHz operation
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Technology
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- .09 micron, 9-layer Cu metal, CMOS process
- 1.0 GHz and 1.2 GHz frequency
- 72 watt typical, 79 watt peak power consumption
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