Overview Features Tech Specs Resources Specifications UltraSPARC T1 Processor Technical Documentation Key Specifications 16 KB primary instruction cache per core 3 MB unifed level 2 cache Up to 8 cores, 4 threads per core Details CPU Caches Integration Technology CPU   UltraSPARC Architecture 2005 (SPARC V9 compliant) On-chip level 2 cache Public key encryption support (RSA) 48-bit virtual, 40-bit physical address space Support for four page sizes: 8K, 64K, 4M, 256M Support for Hypervisor 4, 6, or 8 core versions Caches   16 KB primary instruction cache per core - Parity protected and single-bit error recoverable - 4-way set-associative 8 KB primary data cache per core - Parity protected and single-bit error recoverable - 4-way set-associative 3 MB unifed level 2 cache - 12-way set associative, 4 banks - ECC Integration   Up to 8 cores, 4 threads per core 4 144-bit DDR2-533 SDRAM interfaces - Quad error correct, octal error detect, chipkill ECC 4 DIMMS per controller - 16 DIMMS total Optional 2-channel operation mode JBUS Interface - 3.1 GB/sec peak effective bandwidth - 128 bit address/data bus - 150 - 200 MHz operation Technology   .09 micron, 9-layer Cu metal, CMOS process 1.0 GHz and 1.2 GHz frequency 72 watt typical, 79 watt peak power consumption